BCM8702 - Serial 10-GbE Transceiver with XAUI™ Interface

Serial 10-GbE Transceiver with XAUI™ Interface

The BCM8702 Ethernet LAN PHY is a fully integrated serialization/deserialization (10.3125 Gbps) interface device performing the extension functions for a 10.3125 Gbps Serial Ethernet Reconciliation Sublayer (RS) interface. The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data Recovery (CDR).

On-chip clock synthesis is performed by the high frequency, low-jitter, phase-locked loops for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing the on-chip VCOs directly to their respective incoming data streams. Elastic buffers allow the XAUI and PMD interfaces to operate in either a synchronous or asynchronous configuration. An external 156.25- MHz VCXO is required for synchronous mode operation or for asynchronous mode with clock cleanup.

  • IEEE 802.3ae compliant
  • Support for XENPAK and XGP Standards
  • Power supplies: core, LVPECL, CML, and XAUI at 1.8V, MDIO at 1.2V, and CMOS at 1.8 or 3.3V.
  • Low power consumption eliminates external heat sinks, fans for system airflow, and expensive high current power supplies.